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Please use this identifier to cite or link to this item: http://dspace.cityu.edu.hk/handle/2031/9362
Title: Post-Quantum Cryptographic Hardware Design
Authors: Li, Guangyan
Department: Department of Electrical Engineering
Issue Date: 2020
Supervisor: Supervisor: Dr. Cheung, Ray C C; Assessor: Dr. Cheng, Lee Ming
Abstract: With the fast development of quantum computing in recent decades, the demand for the novel post­quantum cryptographic method has been triggered. Including the National Institute of Standards and Technology (NIST) and the PQCRYPTO project funded by the EU, many standards bodies and government institutions have announced their intentions on Post­Quantum Cryptography. Lots of novel cryptography schemes offering quantum­resistance have been published, for instance, the NewHope, the NTRU, the Ring Learning­With­Error (RLWE). Besides, the development of the Internet­of­Things (IoT) is stimulating the demand on low­cost and lightweight hardware architecture. However, there is still no lightweight post­quantum cryptographic standard. Fortunately, there is a light­weighted variant of the RLWE called the Binary Ring Learning­With­Error(BRLWE) proposed by changing the digits of keys from 2­byte into binary without significant security level distortion. To fill in the gap, the final year student designed a lightweight System­on­Chip (SoC) platform based on an open­sourced RISCV processor from Clifford Wolf’s Picorv32 project. The BRLWE cryptography is implemented on the SoC platform in C language, with key length = 256 bits because of the limitation of SoC platform. Besides, a novel variant of BRLWE algorithm with replaced parameter set would be proposed, which is optimized to be friendly with number theoretic transform (NTT) multiplication in order to accelerate the processing time without changing the key size. Then the SoC platform is implemented onto a 12MHz Lattice iCE40­ HX8K FPGA development kit board consuming 7353 Logic Cells in total. The average process­ ing time for the original parameter set (including the key generation, encryption and decryption) is 26.562 seconds. And the average processing time of the variant of BRLWE algorithm with the novel parameter scheme and NTT multiplication (including the key generation, encryption and decryption) is 11.238 seconds.
Appears in Collections:Electrical Engineering - Undergraduate Final Year Projects 

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