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DC Field | Value | Language |
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dc.contributor.author | Ip, Tsz Yin | en_US |
dc.date.accessioned | 2013-08-26T08:03:01Z | |
dc.date.accessioned | 2017-09-19T09:14:10Z | |
dc.date.accessioned | 2019-02-12T07:32:20Z | - |
dc.date.available | 2013-08-26T08:03:01Z | |
dc.date.available | 2017-09-19T09:14:10Z | |
dc.date.available | 2019-02-12T07:32:20Z | - |
dc.date.issued | 2013 | en_US |
dc.identifier.other | 2013eeity978 | en_US |
dc.identifier.uri | http://144.214.8.231/handle/2031/7070 | - |
dc.description.abstract | Due to the increases of the uses of computing device, there is a raise of the attention to computing security. A secure processor is an advance secure issue which provides a trusted platform in a hardware manner. The hardware-based secure process is able to resist from both software and hardware malicious attacks. The encryption stage is a key element of the secure issue and a Random Number Generator stands as a key point in this stage by providing a random encryption key. Therefore, a True Random Number Generator (TRNG) is studied in this project. The design is a ring-oscillator sourced TRNG and it is implemented on a Xilinx Sparatan-6 Field-programmable Gate Array (FGPA) board. The output of the TRNG is captured and feed-back to the computer side via UART for the testing purpose. MicroBlaze, a softcore processor, is used for the capture and feed-back. The output of the design is verified by the two tests suits, the DIEHARD tests suite and the NIST RNG tests suite. The design of the TRNG is modified by adjusting the number of ring oscillator and D Flip-Flop and optimized in terms of operating frequency in order to obtain a high speed and trusted TRNG. | en_US |
dc.rights | This work is protected by copyright. Reproduction or distribution of the work in any format is prohibited without written permission of the copyright owner. | en_US |
dc.rights | Access is restricted to CityU users. | en_US |
dc.title | FPGA-based Secure Processor | en_US |
dc.contributor.department | Department of Electronic Engineering | en_US |
dc.description.supervisor | Supervisor: Dr. Leung, AnDr.ew C S; Assessor: Dr. Cheung, Ray C C | en_US |
Appears in Collections: | Electrical Engineering - Undergraduate Final Year Projects |
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fulltext.html | 146 B | HTML | View/Open |
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