An object-oriented processor design based on HDL

Ho, Ka Chung

Please use this identifier to cite or link to this item: http://dspace.cityu.edu.hk/handle/2031/6389

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DC Field	Value	Language
dc.contributor.author	Ho, Ka Chung	en_US
dc.date.accessioned	2011-09-15T01:51:40Z
dc.date.accessioned	2017-09-19T09:12:22Z
dc.date.accessioned	2019-02-12T07:29:56Z	-
dc.date.available	2011-09-15T01:51:40Z
dc.date.available	2017-09-19T09:12:22Z
dc.date.available	2019-02-12T07:29:56Z	-
dc.date.issued	2011	en_US
dc.identifier.other	2011eehkc038	en_US
dc.identifier.uri	http://144.214.8.231/handle/2031/6389	-
dc.description.abstract	High Level Instruction Set Computer (HISC) is a computer architecture that uses the operand descriptor to support the Object-Oriented Programming in hardware level. jHISC is a 32-bit processor that implements HISC architecture. In this project, the processer based on the jHISC V4 architecture is pipelined and is implemented in Verilog. The object cache and the object buffer are enhanced, and the branch predictor is added to utilize the pipeline. The performance of the processor is improved compared with the previous version if the required data exists in the object buffer. In fact, the bottleneck still exists between the object buffer and the object cache.	en_US
dc.rights	This work is protected by copyright. Reproduction or distribution of the work in any format is prohibited without written permission of the copyright owner.	en_US
dc.rights	Access is restricted to CityU users.	en_US
dc.title	An object-oriented processor design based on HDL	en_US
dc.contributor.department	Department of Electronic Engineering	en_US
dc.description.supervisor	Supervisor: Dr. Fong, Anthony S S; Assessor: Dr. Wong, K W	en_US
Appears in Collections:	Electrical Engineering - Undergraduate Final Year Projects

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