Design and simulation of multi-GHz flip-flops

Abstract

CMOS is one of the common technologies which are used to make the semiconductors and to develop the integrated circuits, such as processors, chipsets and memory circuits. CMOS memory circuits are treated as the main products in the world and are expanded widely to satisfy various requirements in operational speed, high power, the size of transistors and some environmental tolerance. This aims of this project is to study and design a sense amplifier (SA) for flip flop circuit application. The schematic is developed and then the simulation, following the procedures of CMOS design flow is conducted. This report presents various methods for analyzing the characteristics of SA. The focus is placed on the improvement of the operation speed and the dynamic power dissipation. The final design of SA circuit is realized with 0.18µm CMOS technology. The simulation includes data rate, dynamic power dissipation, delay under different data activities to have more accurate. For the results of power dissipation, it shows that the internal power correlates with α and the best performances are conducted at PDP simulation. The simulation results suggest that the SA is suitable for using in the applications of high performance and low power.